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MC9S12HZ256CPV Freescale飛思卡爾16位微控制器LQFP 112腳綠色環(huán)保封裝形式，工作溫度-45℃-855℃

The MC9S12HZ256CPV microcontroller units (MCU) are 16-bit devices composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B software compatible modules (MSCAN). In addition, they feature a 32x4 liquid crystal display (LCD) controller/driver, a pulse width modulator motor controller (MC) consisting of 16 high current outputs suited to drive up to four stepper motors, and four stepper stall detectors (SSD) to simultaneously calibrate the pointer position of each motor. System resource mapping, clock generation,interrupt control, and external bus interfacing are managed by the HCS12 Core. The MC9S12HZ256CPV have full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 8 general-purpose I/O pins are available with interrupt and wake-up capability from stop or wait mode.

MC9S12HZ256CPV 特性

• HCS12 core
  – 16-bit HCS12 CPU
  Upward compatible with M68HC11
  Interrupt stacking and programmer’s
  16-bit ALU
  Instruction queue
  Enhanced indexed addressing
  – MEBI (multiplexed external bus interface)
  – MMC (module mapping control)
  – INT (interrupt control)
  – DBG (debugger and breakpoints)
  – BDM (background debug mode)? Memory
  – 256K, 128K, 64K, 32K Flash EEPROM or ROM
  – 2K, 1K byte EEPROM
  – 12K, 6K, 4K, 2K byte RAM
• CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
• Analog-to-digital converter
  – 16 channels, 10-bit resolution
  – External conversion trigger capability
• Two 1-Mbps, CAN 2.0 A, B software compatible modules
  – Five receive and three transmit buffers
  – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
  – Four separate interrupt channels for Rx, Tx, error and wake-up
  – Low-pass filter wake-up function
  – Loop-back for self test operation
• Timer
  – 16-bit main counter with 7-bit prescaler
  – 8 programmable input capture or output compare channels
  – Two 8-bit or one 16-bit pulse accumulators
• 6 PWM channels
  – Programmable period and duty cycle
  – 8-bit 6-channel or 16-bit 3-channel
  – Separate control for each pulse width and duty cycle
  – Center-aligned or left-aligned outputs
  – Programmable clock select logic with a wide range of frequencies
  – Fast emergency shutdown input
• Serial interfaces
  – Two asynchronous serial communications interfaces (SCI)
  – Synchronous serial peripheral interface (SPI)
  – Inter-integrated circuit interface (IIC)
• Liquid crystal display (LCD) driver with variable input voltage
  – Configurable for up to 32 frontplanes and 4 backplanes or general-purpose input or output
  – 5 modes of operation allow for different display sizes to meet application requirements
  – Unused frontplane and backplane pins can be used as general-purpose I/O
• PWM motor controller (MC) with 16 high current drivers
  – Each PWM channel switchable between two drivers in an H-bridge configuration
  – Left, right and center aligned outputs
  – Support for sine and cosine drive
  – Dithering
  – Output slew rate control
• Four stepper stall detectors (SSD)
  – Full step control during return to zero
  – Voltage detector and integrator / sigma delta converter circuit
  – 16-bit accumulator register
  – 16-bit modulus down counter
  112-pin LQFP and 80-pin QFP packages
  – 85 I/O lines with 5-V input and drive capability
  – 5-V A/D converter inputs
  – 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger
  Operation at 50 MHz equivalent to 25-MHz bus speed
  ? Development support
  – Single-wire background debug? mode (BDM)
  – Debugger and on-chip hardware breakpoints

MC9S12HZ256CPV 產(chǎn)品區(qū)別

MC9S12HZ256 選型

MC9S12HZ256CPV 技術(shù)支持

• MC9S12HZ256CPV 英文數(shù)據(jù)手冊 . PDF
• MC9S12HZ256CPV 選型指南 . xls (內(nèi)附參考設(shè)計(jì)參考價(jià)格)
• MC9S12HZ256CPV 封裝形式 .jpg
• 可升級的汽車儀表解決方案 . PDF